Demonstrator system is composed of Bumblebee BBX3 stereo-vision camera, Cyclone V heterogeneous SoC development kit and OpenGL-based host demonstrator. The developed technology targets high computational performance while having low-power consumption and overall costs. The SoC software application ensures image acquisition via PCIe, control of FPGA accelerator pipeline and dispatching processed images to PC-based demonstrator via ethernet. All disparity-related computations are carried out on FPGA logic (schematic described in VHDL), this includes interpolation of Bayer filter mosaic, correction for barrel distortions, rectification, feature extraction and disparity calculation.
Although, the system is constantly improved and new computational approaches are being researched, the developed technology already can be used for depth sensing applications in power-critical systems such as mobile drones and some IoT use-cases.
Key performance indicators:
– power: <5w (processing)
– framerate: up to 70fps@1MP
– disparity range: 128 pixels
